CXSD62117双通道电压模式和同步PWM控制器驱动双N通道mosfet两个通道均采用180度相移

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发表时间：2020-04-24浏览次数：156

CXSD62117双通道电压模式和同步PWM控制器驱动双N通道mosfet两个通道均采用180度相移

目录vRV嘉泰姆

1.产品概述         2.产品特点
3.应用范围       4.下载产品资料PDF文档
5.产品封装图                     6.电路原理图
7.功能概述       8.相关产品

一,产品概述(General Description) vRV嘉泰姆
The CXSD62117 is a dual channel voltage mode and syn-chronousvRV嘉泰姆
PWM controller which drives dual N-channel MOSFETs. The two channelsvRV嘉泰姆
are operated with 180 de-gree phase shift.The device integrates all of thevRV嘉泰姆
control, monitoring, and protecting functions into a single package; providesvRV嘉泰姆
two controlled power output with over-voltage, over-temperature, andvRV嘉泰姆
over-current protections.vRV嘉泰姆
The CXSD62117 provides excellent regulation for output load variation.vRV嘉泰姆
The internal 1.0V temperature-compen- sated reference voltage providesvRV嘉泰姆
high accuracy of 0.8% over line and temperature. The device includes avRV嘉泰姆
50kHz free-running triangle-wave oscillator that is adjustable from 50kHzvRV嘉泰姆
to 400kHz.The CXSD62117 has been equipped with excellent pro-tectionvRV嘉泰姆
functions: POR, OCP, UVP, and OVP protections.The Power-On-Reset (POR)vRV嘉泰姆
circuit can monitor the VCC and OCSET voltage to make sure the supplyvRV嘉泰姆
voltage ex-ceeds their threshold voltage while the controller is running. ThevRV嘉泰姆
Over-Current Protection (OCP) monitors the output current by using thevRV嘉泰姆
voltage drop across the high side MOSFET’s RDS(ON). When the outputvRV嘉泰姆
current reaches the trip point, the controller will be latched. Under-VoltagevRV嘉泰姆

Protection (UVP) and Over-Voltage Protection (OVP) moni-tor the FBvRV嘉泰姆
voltage to protect CXSD62117 from burnout when output voltage isvRV嘉泰姆
under 50% or over 120% of normal out-put voltage. The CXSD62117vRV嘉泰姆
is available in SOP-20 package.vRV嘉泰姆

二.产品特点(Features)vRV嘉泰姆
Single 12V Power Supply RequiredvRV嘉泰姆
Excellent Output Voltage RegulationvRV嘉泰姆
- 1.0V±0.8% Internal Reference Over Line and TemperaturevRV嘉泰姆
Simple Single Loop Control DesignvRV嘉泰姆
- Voltage Mode PWM Control 0~100% Duty RatiovRV嘉泰姆
Programmable Frequency Range from 50kHz tovRV嘉泰姆
400kHz (Constant 50kHz when Floating)vRV嘉泰姆
Integrated Soft-Start and Soft-Off (Patent Pending)vRV嘉泰姆
Support Pre-Biased Power-OnvRV嘉泰姆
Both Channel with 180o Phase ShiftvRV嘉泰姆
Integrated Boot-Strap DiodevRV嘉泰姆
Over-Current ProtectionvRV嘉泰姆
- Sense High Side MOSFET’s RDS(ON)vRV嘉泰姆
120% Over-Voltage ProtectionvRV嘉泰姆
50% Under-Voltage ProtectionvRV嘉泰姆
Over-Temperature ProtectionvRV嘉泰姆
Available in SOP-20 PackagevRV嘉泰姆
Lead Free and Green Devices Available (RoHS Compliant)vRV嘉泰姆
三,应用范围 (Applications)vRV嘉泰姆
SMPSvRV嘉泰姆

四.下载产品资料PDF文档 vRV嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！vRV嘉泰姆

QQ截图20160419174301.jpg vRV嘉泰姆

vRV嘉泰姆

五,产品封装图 (Package)vRV嘉泰姆

vRV嘉泰姆

六.电路原理图vRV嘉泰姆

vRV嘉泰姆

七,功能概述vRV嘉泰姆

Layout ConsiderationvRV嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thevRV嘉泰姆
regulator. With power devices switching at 200kHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting imped- ances and the magnitude of voltage spike. And signal and power grounds are to be kept separating till com-bined using the ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold linesvRV嘉泰姆
Layout Consideration (Cont.)vRV嘉泰姆

indicating high current paths; these traces must be short and wide. Components along the bold lines should bevRV嘉泰姆

placed lose together. Below is a checklist for your layout:- Keep the switching nodes (UGATE, LGATE, and PHASE)away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep tracesvRV嘉泰姆
to these nodes as short as possible.vRV嘉泰姆
- The traces from the gate drivers to the MOSFETs (UGATEand LGATE) should be short and wide.vRV嘉泰姆

- Place the source of the high-side MOSFET and the drainof the low-side MOSFET as close as possible. Minimiz-ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.vRV嘉泰姆

- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closevRV嘉泰姆

their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET asvRV嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).vRV嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thevRV嘉泰姆
loads. The input capacitor GND should be close to the lower MOSFET GND.vRV嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes)should be a large plane for heat sinking.vRV嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.vRV嘉泰姆
- The decoupling capacitor for VCC should be placed near the VCC and GND. CBOOT should be connected asvRV嘉泰姆
close to the BOOT and PHASE pins as possible. vRV嘉泰姆

八,相关产品 更多同类产品...... vRV嘉泰姆

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CXSD6276vRV嘉泰姆	SOP-8vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	20vRV嘉泰姆	2.2vRV嘉泰姆	13.2vRV嘉泰姆	0.8vRV嘉泰姆	5~12vRV嘉泰姆	2100vRV嘉泰姆
CXSD6276AvRV嘉泰姆	SOP-8vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	20vRV嘉泰姆	2.2vRV嘉泰姆	13.2vRV嘉泰姆	0.8vRV嘉泰姆	5~12vRV嘉泰姆	2100vRV嘉泰姆
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CXSD6278vRV嘉泰姆	SOP-8vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	10vRV嘉泰姆	3.3vRV嘉泰姆	5.5vRV嘉泰姆	0.8vRV嘉泰姆	5vRV嘉泰姆	2100vRV嘉泰姆
CXSD6279BvRV嘉泰姆	SOP-14vRV嘉泰姆	VM vRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	10vRV嘉泰姆	5vRV嘉泰姆	13.2vRV嘉泰姆	0.8vRV嘉泰姆	12vRV嘉泰姆	2000vRV嘉泰姆
CXSD6280vRV嘉泰姆	TSSOP-24vRV嘉泰姆 \|QFN5x5-32vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	2vRV嘉泰姆	20vRV嘉泰姆	5vRV嘉泰姆	13.2vRV嘉泰姆	0.6vRV嘉泰姆	5~12vRV嘉泰姆	4000vRV嘉泰姆
CXSD6281NvRV嘉泰姆	SOP14vRV嘉泰姆 QSOP16vRV嘉泰姆 QFN-16vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	30vRV嘉泰姆	2.9vRV嘉泰姆	13.2vRV嘉泰姆	0.9vRV嘉泰姆	12vRV嘉泰姆	4000vRV嘉泰姆
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CXSD6283vRV嘉泰姆	SOP-14vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	25vRV嘉泰姆	2.2vRV嘉泰姆	13.2vRV嘉泰姆	0.8vRV嘉泰姆	12vRV嘉泰姆	5000vRV嘉泰姆
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CXSD6286vRV嘉泰姆	SOP-14vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	1vRV嘉泰姆	10vRV嘉泰姆	5vRV嘉泰姆	13.2vRV嘉泰姆	0.8vRV嘉泰姆	12vRV嘉泰姆	3000vRV嘉泰姆
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CXSD6288vRV嘉泰姆	SSOP28vRV嘉泰姆 QFN4x4-24vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	2vRV嘉泰姆	20vRV嘉泰姆	5vRV嘉泰姆	24vRV嘉泰姆	0.9vRV嘉泰姆	5vRV嘉泰姆	1200vRV嘉泰姆
CXSD6289vRV嘉泰姆	SOP-20vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	2vRV嘉泰姆	20vRV嘉泰姆	2.2vRV嘉泰姆	13.2vRV嘉泰姆	0.6vRV嘉泰姆	5~12vRV嘉泰姆	4000vRV嘉泰姆
CXSD6290vRV嘉泰姆	SOP8\|DFN3x3-10vRV嘉泰姆	VMvRV嘉泰姆	1vRV嘉泰姆	2vRV嘉泰姆	-vRV嘉泰姆	-vRV嘉泰姆

上一篇：CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式

下一篇：CXSD62118单相恒定时间同步的PWM控制器驱动N通道mosfet低压芯片组RAM电源

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