CXTP65160 CXTP65161 CXTP65162是一种简单、经济、高速的线性稳压器，用于在双数据率（DDR）存储系统中产生终端电压，以满足JEDEC SSTL_和SSTL_或其他特定接口（如HSTL、SCSI-2和SCSI-3等）的设备要求。该稳压器能够在将输出电压调节到40毫伏以内的同时，主动吸收或吸收高达2A的电压。输出端电压cab通过两个外部分压电阻器严格调节到跟踪1/2VDDQ，或通过外部施加REFEN pin电压来编程所需的输出电压。CXTP65162 CXTP65161 CXTP65160还集成了一个高速差分放大器，以在线路/负载瞬态中提供超快响应。其它特性包括极低的初始偏置电压、良好的负载调节、双向限流和片上热关机保护。CXTP65162 CXTP65161 CXTP65160在PSOP-8（外露衬垫）表面安装包中提供
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产品概述 返回TOP
The CXTP65162 CXTP65161 CXTP65160 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage. The CXTP65162 CXTP65161 CXTP65160 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The CXTP65162 CXTP65161 CXTP65160 are available in the PSOP-8 (Exposed Pad) surface mount packages.
产品特点 返回TOP
Ideal for DDR-I, DDR-II and DDR-III VTT Applications
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Voltage traces REFEN Pin Voltage.
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
Current Limiting Protection
Thermal Shutdown Protection
PSOP-8 with exposed pad Pb-Free Package.
应用范围 返回TOP
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
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产品封装图 返回TOP
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DDR Bus Termination Regulator（DDR总线终端稳压器） |
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Product |
Status |
Output Offset Voltage |
Load Reg. |
Max Sink& Source Current |
VIN Max |
Control Voltage Range |
|
NRFND |
±20mV |
0.8%,1.2% |
3A |
6V |
3.3V to 6V |
|
|
Active |
±20mV |
0.50% |
1.5 |
6V |
3.3V to 6V |
|
|
Active |
±20mV |
0.50% |
2A |
6V |
3.3V to 6V |
|
