目录buV嘉泰姆

1.产品概述                       2.产品特点buV嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 buV嘉泰姆
5.产品封装图                     6.电路原理图                   buV嘉泰姆
7.功能概述                        8.相关产品buV嘉泰姆

一,产品概述(General Description)    buV嘉泰姆

  The CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. The CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in notebook computers.buV嘉泰姆
  The CXSD62102A provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), the CXSD62102A provides very high efficiency over light to heavy loads with loading-buV嘉泰姆
modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements.buV嘉泰姆
  The CXSD62102A is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for NB applications. The Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The CXSD62102A has a 1ms digital soft start and built-in an integrated output discharge device for soft stop. An internal integrated soft-buV嘉泰姆
start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors.buV嘉泰姆
  The CXSD62102A is available in 16pin TQFN3x3-16 package respectively.buV嘉泰姆
二.产品特点(Features)buV嘉泰姆

Adjustable Output Voltage from +0.6V to +3.3VbuV嘉泰姆
- 0.6V Reference VoltagebuV嘉泰姆
- ±0.6% Accuracy Over-TemperaturebuV嘉泰姆
Operates from An Input Battery Voltage Range ofbuV嘉泰姆
+1.8V to +28VbuV嘉泰姆
REFIN Function for Over-clocking Purpose frombuV嘉泰姆
0.5V~2.5V rangebuV嘉泰姆
Power-On-Reset Monitoring on VCC pinbuV嘉泰姆
Excellent line and load transient responsesbuV嘉泰姆
PFM mode for increased light load efficiencybuV嘉泰姆
Programmable PWM Frequency from 100kHz to 500kHzbuV嘉泰姆
Built in 30A Output current driving capabilitybuV嘉泰姆
Integrate MOSFET DriversbuV嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETbuV嘉泰姆
Power Good MonitoringbuV嘉泰姆
70% Under-Voltage ProtectionbuV嘉泰姆
125% Over-Voltage ProtectionbuV嘉泰姆
TQFN3x3-16 PackagebuV嘉泰姆
Lead Free and Green Devices Available (RoHS Compliant)buV嘉泰姆
三,应用范围 (Applications)buV嘉泰姆

NotebookbuV嘉泰姆
Table PCbuV嘉泰姆
Hand-Held PortablebuV嘉泰姆
AIO PCbuV嘉泰姆

四.下载产品资料PDF文档 buV嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！buV嘉泰姆

 buV嘉泰姆

五,产品封装图 (Package)buV嘉泰姆

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六.电路原理图buV嘉泰姆

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七,功能概述buV嘉泰姆

Input Capacitor Selection (Cont.)buV嘉泰姆
higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2,buV嘉泰姆
where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current.buV嘉泰姆
For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be-buV嘉泰姆
tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout.buV嘉泰姆
MOSFET SelectionbuV嘉泰姆
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs shouldbuV嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:buV嘉泰姆
For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driverbuV嘉泰姆
will not charge the miller capacitor of this MOSFET.In the turning off process of the low-side MOSFET, thebuV嘉泰姆
load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capaci-buV嘉泰姆
tor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low-buV嘉泰姆
side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFETbuV嘉泰姆
will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con-buV嘉泰姆
verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. ThebuV嘉泰姆
high-side MOSFET does not have this zero voltage switch-ing condition; in addition, it conducts for less time com-buV嘉泰姆
pared to the low-side MOSFET, so the switching loss tends to be dominant. Priority should be given to thebuV嘉泰姆
MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.buV嘉泰姆
The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci-buV嘉泰姆
tance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components:buV嘉泰姆
conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximatelybuV嘉泰姆
given by the following equations:buV嘉泰姆
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSWbuV嘉泰姆
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)buV嘉泰姆
Where TC is the temperature dependency of RDS(ON)FSW is the switching frequencybuV嘉泰姆
tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses whilebuV嘉泰姆
the high-side MOSFET includes an additional transition loss. The switching interval, tSW, is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. buV嘉泰姆
Layout ConsiderationbuV嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.buV嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike acrossbuV嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionbuV嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,buV嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasiticbuV嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short andbuV嘉泰姆
wide printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike.buV嘉泰姆
Besides, signal and power grounds are to be kept sepa- rating and finally combined using ground plane construc-buV嘉泰姆
tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega-buV嘉泰姆
tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are notbuV嘉泰姆
recommended. Below is a checklist for your layout:· Keep the switching nodes (UGATE, LGATE, BOOT,buV嘉泰姆
and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals.buV嘉泰姆
Therefore, keep traces to these nodes as short asbuV嘉泰姆
side MOSFET. On the other hand, the PGND trace should be a separate trace and independently go tobuV嘉泰姆
the source of the low-side MOSFET. Besides, the cur-rent sense resistor should be close to OCSET pin tobuV嘉泰姆
avoid parasitic capacitor effect and noise coupling.buV嘉泰姆
· Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example,buV嘉泰姆
place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)buV嘉泰姆
· The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capaci-buV嘉泰姆
tors should be close to the loads. The input capaci-tor’s ground should be close to the grounds of thebuV嘉泰姆
output capacitors and low-side MOSFET.buV嘉泰姆
· Locate the resistor-divider close to the FB pin to mini-mize the high impedance trace. In addition, FB pinbuV嘉泰姆
traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE).buV嘉泰姆

Layout Consideration (Cont.)buV嘉泰姆

possible and there should be no other weak signal traces in parallel with theses traces on any layer.buV嘉泰姆
· The signals going through theses traces have both high dv/dt and high di/dt with high peak charging andbuV嘉泰姆
discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be shortbuV嘉泰姆
and wide.buV嘉泰姆
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible.buV嘉泰姆
Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce ofbuV嘉泰姆
the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking.buV嘉泰姆

· The PGND is the current sensing circuit reference ground and also the power ground of the LGATE low-buV嘉泰姆

• CXSD62102ACXSD62102AbuV嘉泰姆

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