目录a1h嘉泰姆

1.产品概述                       2.产品特点a1h嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 a1h嘉泰姆
5.产品封装图                     6.电路原理图                   a1h嘉泰姆
7.功能概述                        8.相关产品a1h嘉泰姆

一,产品概述(General Description)         a1h嘉泰姆

  The CXSD6296 CXSD6296A JTMA872B CXSD6296C CXSD6296D is a voltage mode, fixed 200kHz/300kHz/600kHz switching frequency, synchronous buck converter.The CXSD6296 allows wide input voltage that is either a single 5~12V or two supply voltage(s) for various applications. A power-on-reset (POR) circuit monitors the VCC supply voltage to prevent wrong logic controls. A built-in soft-start circuit prevents the output voltages from over-shoot as well as limits the input current. An internal 0.6V temperature-ompensated reference voltage with high accuracy is designed to meet the requirement of low out-put voltage applications. The CXSD6296 provides excel-lent output voltage regulations against load current variation.a1h嘉泰姆
   The controller’s over-current protection monitors the out-put current by using the voltage drop across the RDS (ON) of low-side MOSFET, eliminating the need for a cur-rent sensing resistor that features high efficiency and low cost. In  addition, the CXSD6296 also integrates excel-lent protection functions. The over-voltage protection (OVP) , under-voltage protection (UVP). OVP circuit which moni-tors the FB voltage to prevent the PWM output from over voltage, and UVP circuit which monitors the FB voltage to prevent the PWM output from under voltage or short circuit.a1h嘉泰姆
  The CXSD6296 is available in SOP-8P packagesa1h嘉泰姆
二.产品特点(Features)a1h嘉泰姆

1.）Wide 5V to 12V Supply Voltagea1h嘉泰姆
2.）Power-On-Reset Monitoring on VCCa1h嘉泰姆
3.）Excellent Output Voltage Regulationsa1h嘉泰姆
      - 0.6V Internal Reference for CXSD6296/A/Da1h嘉泰姆
      - 0.8V Internal Reference for CXSD6296B/Ca1h嘉泰姆
      - ±0.6% Over-Temperature Rangea1h嘉泰姆
4.）Integrated Soft-Starta1h嘉泰姆
5.）Voltage Mode PWM Operation with External Compensationa1h嘉泰姆
6.）Up to 90% Duty Ratio for Fast Transient Responsea1h嘉泰姆
7.）Constant Switching Frequencya1h嘉泰姆
      - 300kHz ±10% for CXSD6296/Ba1h嘉泰姆
      - 200kHz ±10% for CXSD6296Ca1h嘉泰姆
      - 600kHz ±10% for CXSD6296A/Da1h嘉泰姆
8.）Integrated Bootstrap Forward P-CH MOSFETa1h嘉泰姆
9.）50% Under-Voltage Protectiona1h嘉泰姆
10.）125% Over-Voltage Protectiona1h嘉泰姆
11.）Adjustable Over-Current Protection Thresholda1h嘉泰姆
       - Using the RDS(ON) of Low-Side MOSFETa1h嘉泰姆
12.）Shutdown Control by COMP SOP-8P Packagea1h嘉泰姆
13.）Lead Free and Green Devices Availablea1h嘉泰姆
三,应用范围 (Applications)a1h嘉泰姆

Graphic Cardsa1h嘉泰姆
DSL, Switch HUBa1h嘉泰姆
Wireless Lana1h嘉泰姆
Notebook Computera1h嘉泰姆
Mother Boarda1h嘉泰姆
LCD Monitor/TVa1h嘉泰姆
四.下载产品资料PDF文档 a1h嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！a1h嘉泰姆

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五,产品封装图 (Package)a1h嘉泰姆

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六.电路原理图a1h嘉泰姆

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七,功能概述a1h嘉泰姆

In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thea1h嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spikea1h嘉泰姆
across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-offa1h嘉泰姆
transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off,a1h嘉泰姆
current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Anya1h嘉泰姆
parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general,a1h嘉泰姆
using short and wide printed circuit traces should minimize interconnecting imped ances and the magnitudea1h嘉泰姆
of voltage spike. And signal and power grounds are to be kept separate till combined using ground planea1h嘉泰姆
construction or single point grounding. Figure 8. illustrates the layout, with bold lines indicating high currenta1h嘉泰姆
paths; these traces must be short and wide. Components along the bold lines should be placed lose together.a1h嘉泰姆
Below is a checklist for your layout:a1h嘉泰姆
- Keep the switching nodes (UGATE, LGATE, and PHASE)away from sensitive small signal nodes since thesea1h嘉泰姆
nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.a1h嘉泰姆
- The traces from the gate drivers to the MOSFETs (UGand LG) should be short and wide.a1h嘉泰姆
- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-a1h嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.a1h嘉泰姆
- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closea1h嘉泰姆
their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET asa1h嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).a1h嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thea1h嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.a1h嘉泰姆
The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.a1h嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.a1h嘉泰姆

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