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CXSD6280两个同步降压型脉宽调制控制器高精度内部参考电压的线性控制器PWM控制器同步buck拓扑中的两个N沟道mosfet
发表时间:2020-04-21浏览次数:154
CXSD6280两个同步降压型脉宽调制控制器高精度内部参考电压的线性控制器PWM控制器同步buck拓扑中的两个N沟道mosfet
 

目录cj2嘉泰姆

1.产品概述                       2.产品特点cj2嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 cj2嘉泰姆
5.产品封装图                     6.电路原理图                   cj2嘉泰姆
7.功能概述                        8.相关产品cj2嘉泰姆

一,产品概述(General Description)         cj2嘉泰姆


          The CXSD6280 has two synchronous buck PWM control-lerscj2嘉泰姆
and one linear controller with high precision internal references voltagecj2嘉泰姆
to offer accurate outputs. The PWM controllers are designed to drivecj2嘉泰姆
two N-channel MOSFETs in synchronous buck topology, and the linearcj2嘉泰姆
controller drives an external N-channel MOSFET. The device re-quirescj2嘉泰姆
12V and 5V power supplies, if the 5V supply is not available, VCC12 cancj2嘉泰姆
offer an optional shunt regulator 5.8V for 5V supply.All outputs havecj2嘉泰姆
independent soft-start and enable func-tions by SS/EN pins to control.cj2嘉泰姆
Connect a capacitor from each SS/EN pin to the ground for setting thecj2嘉泰姆
soft-start time, and pulling the SS/EN pin below 1V to disable regulator.cj2嘉泰姆
Pull the SS2/EN2 to VCC, enter the DDR mode,the SS1/EN1 controlscj2嘉泰姆
both VOUT1 and VOUT2, and al-lows VOUT2 to track VOUT1. It alsocj2嘉泰姆
offers the phase shift function by REFOUT pin to select the phase shiftcj2嘉泰姆
between VOUT1 and VOUT2 in DDR mode or Independent mode.cj2嘉泰姆
When all SS/EN pins exceed 3.3V and no faults are detected, the PGOODcj2嘉泰姆
pin goes high to indicate the regu-lators are ready. If any of the SS/EN pinscj2嘉泰姆
goes below 3.2V or any of the outputs has a fault condition, the PGOOD pincj2嘉泰姆
will be pulled low.cj2嘉泰姆
     The internal oscillator is nominally 300kHz (keep the FS/SYNC pin opencj2嘉泰姆
or short to GND), and it offers the pro-grammable frequency function fromcj2嘉泰姆
70kHz to 800kHz; con-necting a resistor from FS/SYNC to VCC12 to decreasecj2嘉泰姆
the frequency, conversely, connect a resistor from FS/SYNC to GND tocj2嘉泰姆
increase the frequency.The IC also pro-vides the synchronous frequencycj2嘉泰姆
function. Connect the LGATE signal of another converter to FS/SYNC pin;cj2嘉泰姆
forc-ing the switching frequency to follow the external clock.
         The possible synchronous frequency is from 150kHz to 800kHz. Therecj2嘉泰姆
is no Rds(on) sensing or under-voltage sens-ing on CXSD6280. However, itcj2嘉泰姆
provides a simple short-circuit protection by monitoring the COMP1 and COMP2cj2嘉泰姆
for over-voltage. When any of two pins exceeds their trip point and the conditioncj2嘉泰姆
persists for 1-2 internal clock cycle (3-6μs at 300kHz), then it will shut downcj2嘉泰姆
all regulators.cj2嘉泰姆
二.产品特点(Features)cj2嘉泰姆


1.)Two Synchronous Buck Converters and A Linear Regulatorcj2嘉泰姆
2.)VIN Range up to 12Vcj2嘉泰姆
3.)Input Power Supplies Require 12V and 5V orcj2嘉泰姆
4.)Use 12V to Generate a Shunt Regulator 5.8Vcj2嘉泰姆
5.)0.6V Reference for VOUT1 and VOUT3 with 0.8% Accuratecj2嘉泰姆
6.)3.3V Reference for VOUT2 with 0.8% Accuratecj2嘉泰姆
7.)Buffered VTT Reference Outputcj2嘉泰姆
8.)Three Outputs have Independent Soft-Start and Enablecj2嘉泰姆
9.)Internal 300kHz Oscillator and Programmablecj2嘉泰姆
10.)Frequency Range from 70 kHz to 800kHzcj2嘉泰姆
11.)Synchronous Switching Frequencycj2嘉泰姆
12.)DDR Mode or Independent Mode Selectioncj2嘉泰姆
13.)Phase Shift Selectioncj2嘉泰姆
14.)Power Good Functioncj2嘉泰姆

15.)Short-Circuit Protection for VOUT1 and VOUT2cj2嘉泰姆
16.)Thermally Enhanced TSSOP-24P and QFN5x5-32 Packagescj2嘉泰姆
17.)Lead Free and Green Devices Available (RoHS Compliant) cj2嘉泰姆
三,应用范围 (Applications)cj2嘉泰姆


Graphic Cardscj2嘉泰姆
DDR memory Power Suppliescj2嘉泰姆
Low-Voltage Distributed Power Suppliescj2嘉泰姆
四.下载产品资料PDF文档 cj2嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持cj2嘉泰姆

 QQ截图20160419174301.jpgcj2嘉泰姆

五,产品封装图 (Package)cj2嘉泰姆


cj2嘉泰姆
FUNCTIONNAMEFUNCTIONcj2嘉泰姆
These pins are the outputs of error amplifiers of their respective regulators. They arecj2嘉泰姆
used to set the compensation components.cj2嘉泰姆
These pins provide two functions. Connect a capacitor to the GND for setting thecj2嘉泰姆
soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable thecj2嘉泰姆
respective output, leave open to enable the respective output.cj2嘉泰姆
These pins provide two functions. Connect a capacitor to the GND for setting thecj2嘉泰姆
soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable thecj2嘉泰姆
respective output, leave open to enable the respective output.cj2嘉泰姆

PINcj2嘉泰姆

FUNCTIONcj2嘉泰姆

NO.cj2嘉泰姆

NAMEcj2嘉泰姆

TSSOP-24Pcj2嘉泰姆

DFN5x5-32cj2嘉泰姆

       

1cj2嘉泰姆

29cj2嘉泰姆

FB1cj2嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.cj2嘉泰姆

2cj2嘉泰姆

30cj2嘉泰姆

COMP1cj2嘉泰姆

These pins are the outputs of error amplifiers of their respective regulators. They are used to set the compensation components.cj2嘉泰姆

3cj2嘉泰姆

31cj2嘉泰姆

COMP2cj2嘉泰姆

4cj2嘉泰姆

32cj2嘉泰姆

FB2cj2嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.cj2嘉泰姆

5cj2嘉泰姆

1cj2嘉泰姆

REFINcj2嘉泰姆

This pin is the reference input voltage of error amplifier of the VOUT2. It also provides the voltage into a buffer, which is out on the REFOUT pin.cj2嘉泰姆

6cj2嘉泰姆

3cj2嘉泰姆

REFOUTcj2嘉泰姆

This pin provides a buffed voltage, which is from REFIN pin. In Independent mode, it can be used by other ICs. In DDR mode, it is from the VOUT1, and can be used as the VTT buffer. This pin also uses to select the phase shift (see table1). When this pincj2嘉泰姆
pulls to VCC, the buffer is disabled and the REFOUT is not available for use. It is recommended that a 0.1μF capacitor is connected to the ground for stability.cj2嘉泰姆

7cj2嘉泰姆

4cj2嘉泰姆

SS1/EN1cj2嘉泰姆

These pins provide two functions. Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable the respective output, leave open to enable the respective output.cj2嘉泰姆

8cj2嘉泰姆

5cj2嘉泰姆

SS2/EN2cj2嘉泰姆

9cj2嘉泰姆

6cj2嘉泰姆

SS3/EN3cj2嘉泰姆

10cj2嘉泰姆

7cj2嘉泰姆

VREFcj2嘉泰姆

This pin provides a 3.3V reference voltage, which can be used by the REFIN pin or other ICs as a voltage reference. It is recommended that a 1μF capacitor is connected to ground for stabilitycj2嘉泰姆

11cj2嘉泰姆

8cj2嘉泰姆

DRIVE3cj2嘉泰姆

This pin drives the gate of an external N-channel MOSFET for linear regulator.cj2嘉泰姆

12cj2嘉泰姆

10cj2嘉泰姆

FB3cj2嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.cj2嘉泰姆

13cj2嘉泰姆

11cj2嘉泰姆

FS/SYNCcj2嘉泰姆

This pin is used to adjust the switching frequency. Connecting a resistor from FS/SYNC pin to the ground increases the switching frequency. Conversely,connecting a resistor from this pin to the VCC12 reduces the switching frequency. In addition, this pin also provides synchronous frequency function. An external clock can be fed into this pin, and force the switching frequency to follow the external clock.cj2嘉泰姆

14cj2嘉泰姆

12cj2嘉泰姆

PGOODcj2嘉泰姆

This pin is an open drain device; connect a pull up resistor to the VCC for PGOOD function.cj2嘉泰姆

15cj2嘉泰姆

13cj2嘉泰姆

GNDcj2嘉泰姆

This pin is the signal ground pin. The metal thermal pad under the package is the IC substrate; connects the GND pin and metal thermal pad together on the board, and ties to the good GND plane for electrical and thermal conduction.cj2嘉泰姆

16cj2嘉泰姆

16cj2嘉泰姆

BOOT2cj2嘉泰姆

These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. It can be connected to a power voltage directly, but the difference voltage between the BOOT and VIN must be high enough to drive the upper MOSFETs.cj2嘉泰姆

17cj2嘉泰姆

14cj2嘉泰姆

UGATE2cj2嘉泰姆

These pins provide the gate driver for the upper MOSFETs of VOUT1 and VOUT2.cj2嘉泰姆

18cj2嘉泰姆

18,23cj2嘉泰姆

PGNDcj2嘉泰姆

This pin is the power ground pin for the gate driver and linear driver circuit. It should be tied to the GND.cj2嘉泰姆

19cj2嘉泰姆

20cj2嘉泰姆

LGATE2cj2嘉泰姆

These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2.cj2嘉泰姆

20cj2嘉泰姆

21cj2嘉泰姆

LGATE1cj2嘉泰姆

These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2.cj2嘉泰姆

21cj2嘉泰姆

19, 22cj2嘉泰姆

VCC12cj2嘉泰姆

Power supply input pin. Connect a nominal 12V power supply to this pin for the gate driver. It is recommended that a decoupling capacitor (1 to 10μF) is connected to the GND for noise decoupling.cj2嘉泰姆

六.电路原理图cj2嘉泰姆


blob.pngcj2嘉泰姆

七,功能概述cj2嘉泰姆


Soft-Start/Enablecj2嘉泰姆
The three SS/EN pins control the soft-start and enable or disable the controller. In Independent mode, the threecj2嘉泰姆
regulators all have independent soft-start and enable functions. Connect a soft-start capacitor from each SS/ENcj2嘉泰姆
pin to the GND to set the soft-start interval, and an open drain logic signal for each SS/EN pin will enable or dis-cj2嘉泰姆
able the respective output.cj2嘉泰姆

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