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CXSD6280两个同步降压型脉宽调制控制器高精度内部参考电压的线性控制器PWM控制器同步buck拓扑中的两个N沟道mosfet
发表时间:2020-04-21浏览次数:328
CXSD6280两个同步降压型脉宽调制控制器高精度内部参考电压的线性控制器PWM控制器同步buck拓扑中的两个N沟道mosfet
 

目录jxh嘉泰姆

1.产品概述                       2.产品特点jxh嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 jxh嘉泰姆
5.产品封装图                     6.电路原理图                   jxh嘉泰姆
7.功能概述                        8.相关产品jxh嘉泰姆

一,产品概述(General Description)         jxh嘉泰姆


          The CXSD6280 has two synchronous buck PWM control-lersjxh嘉泰姆
and one linear controller with high precision internal references voltagejxh嘉泰姆
to offer accurate outputs. The PWM controllers are designed to drivejxh嘉泰姆
two N-channel MOSFETs in synchronous buck topology, and the linearjxh嘉泰姆
controller drives an external N-channel MOSFET. The device re-quiresjxh嘉泰姆
12V and 5V power supplies, if the 5V supply is not available, VCC12 canjxh嘉泰姆
offer an optional shunt regulator 5.8V for 5V supply.All outputs havejxh嘉泰姆
independent soft-start and enable func-tions by SS/EN pins to control.jxh嘉泰姆
Connect a capacitor from each SS/EN pin to the ground for setting thejxh嘉泰姆
soft-start time, and pulling the SS/EN pin below 1V to disable regulator.jxh嘉泰姆
Pull the SS2/EN2 to VCC, enter the DDR mode,the SS1/EN1 controlsjxh嘉泰姆
both VOUT1 and VOUT2, and al-lows VOUT2 to track VOUT1. It alsojxh嘉泰姆
offers the phase shift function by REFOUT pin to select the phase shiftjxh嘉泰姆
between VOUT1 and VOUT2 in DDR mode or Independent mode.jxh嘉泰姆
When all SS/EN pins exceed 3.3V and no faults are detected, the PGOODjxh嘉泰姆
pin goes high to indicate the regu-lators are ready. If any of the SS/EN pinsjxh嘉泰姆
goes below 3.2V or any of the outputs has a fault condition, the PGOOD pinjxh嘉泰姆
will be pulled low.jxh嘉泰姆
     The internal oscillator is nominally 300kHz (keep the FS/SYNC pin openjxh嘉泰姆
or short to GND), and it offers the pro-grammable frequency function fromjxh嘉泰姆
70kHz to 800kHz; con-necting a resistor from FS/SYNC to VCC12 to decreasejxh嘉泰姆
the frequency, conversely, connect a resistor from FS/SYNC to GND tojxh嘉泰姆
increase the frequency.The IC also pro-vides the synchronous frequencyjxh嘉泰姆
function. Connect the LGATE signal of another converter to FS/SYNC pin;jxh嘉泰姆
forc-ing the switching frequency to follow the external clock.
         The possible synchronous frequency is from 150kHz to 800kHz. Therejxh嘉泰姆
is no Rds(on) sensing or under-voltage sens-ing on CXSD6280. However, itjxh嘉泰姆
provides a simple short-circuit protection by monitoring the COMP1 and COMP2jxh嘉泰姆
for over-voltage. When any of two pins exceeds their trip point and the conditionjxh嘉泰姆
persists for 1-2 internal clock cycle (3-6μs at 300kHz), then it will shut downjxh嘉泰姆
all regulators.jxh嘉泰姆
二.产品特点(Features)jxh嘉泰姆


1.)Two Synchronous Buck Converters and A Linear Regulatorjxh嘉泰姆
2.)VIN Range up to 12Vjxh嘉泰姆
3.)Input Power Supplies Require 12V and 5V orjxh嘉泰姆
4.)Use 12V to Generate a Shunt Regulator 5.8Vjxh嘉泰姆
5.)0.6V Reference for VOUT1 and VOUT3 with 0.8% Accuratejxh嘉泰姆
6.)3.3V Reference for VOUT2 with 0.8% Accuratejxh嘉泰姆
7.)Buffered VTT Reference Outputjxh嘉泰姆
8.)Three Outputs have Independent Soft-Start and Enablejxh嘉泰姆
9.)Internal 300kHz Oscillator and Programmablejxh嘉泰姆
10.)Frequency Range from 70 kHz to 800kHzjxh嘉泰姆
11.)Synchronous Switching Frequencyjxh嘉泰姆
12.)DDR Mode or Independent Mode Selectionjxh嘉泰姆
13.)Phase Shift Selectionjxh嘉泰姆
14.)Power Good Functionjxh嘉泰姆

15.)Short-Circuit Protection for VOUT1 and VOUT2jxh嘉泰姆
16.)Thermally Enhanced TSSOP-24P and QFN5x5-32 Packagesjxh嘉泰姆
17.)Lead Free and Green Devices Available (RoHS Compliant) jxh嘉泰姆
三,应用范围 (Applications)jxh嘉泰姆


Graphic Cardsjxh嘉泰姆
DDR memory Power Suppliesjxh嘉泰姆
Low-Voltage Distributed Power Suppliesjxh嘉泰姆
四.下载产品资料PDF文档 jxh嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持jxh嘉泰姆

 QQ截图20160419174301.jpgjxh嘉泰姆

五,产品封装图 (Package)jxh嘉泰姆


jxh嘉泰姆
FUNCTIONNAMEFUNCTIONjxh嘉泰姆
These pins are the outputs of error amplifiers of their respective regulators. They arejxh嘉泰姆
used to set the compensation components.jxh嘉泰姆
These pins provide two functions. Connect a capacitor to the GND for setting thejxh嘉泰姆
soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable thejxh嘉泰姆
respective output, leave open to enable the respective output.jxh嘉泰姆
These pins provide two functions. Connect a capacitor to the GND for setting thejxh嘉泰姆
soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable thejxh嘉泰姆
respective output, leave open to enable the respective output.jxh嘉泰姆

PINjxh嘉泰姆

FUNCTIONjxh嘉泰姆

NO.jxh嘉泰姆

NAMEjxh嘉泰姆

TSSOP-24Pjxh嘉泰姆

DFN5x5-32jxh嘉泰姆

       

1jxh嘉泰姆

29jxh嘉泰姆

FB1jxh嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.jxh嘉泰姆

2jxh嘉泰姆

30jxh嘉泰姆

COMP1jxh嘉泰姆

These pins are the outputs of error amplifiers of their respective regulators. They are used to set the compensation components.jxh嘉泰姆

3jxh嘉泰姆

31jxh嘉泰姆

COMP2jxh嘉泰姆

4jxh嘉泰姆

32jxh嘉泰姆

FB2jxh嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.jxh嘉泰姆

5jxh嘉泰姆

1jxh嘉泰姆

REFINjxh嘉泰姆

This pin is the reference input voltage of error amplifier of the VOUT2. It also provides the voltage into a buffer, which is out on the REFOUT pin.jxh嘉泰姆

6jxh嘉泰姆

3jxh嘉泰姆

REFOUTjxh嘉泰姆

This pin provides a buffed voltage, which is from REFIN pin. In Independent mode, it can be used by other ICs. In DDR mode, it is from the VOUT1, and can be used as the VTT buffer. This pin also uses to select the phase shift (see table1). When this pinjxh嘉泰姆
pulls to VCC, the buffer is disabled and the REFOUT is not available for use. It is recommended that a 0.1μF capacitor is connected to the ground for stability.jxh嘉泰姆

7jxh嘉泰姆

4jxh嘉泰姆

SS1/EN1jxh嘉泰姆

These pins provide two functions. Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable the respective output, leave open to enable the respective output.jxh嘉泰姆

8jxh嘉泰姆

5jxh嘉泰姆

SS2/EN2jxh嘉泰姆

9jxh嘉泰姆

6jxh嘉泰姆

SS3/EN3jxh嘉泰姆

10jxh嘉泰姆

7jxh嘉泰姆

VREFjxh嘉泰姆

This pin provides a 3.3V reference voltage, which can be used by the REFIN pin or other ICs as a voltage reference. It is recommended that a 1μF capacitor is connected to ground for stabilityjxh嘉泰姆

11jxh嘉泰姆

8jxh嘉泰姆

DRIVE3jxh嘉泰姆

This pin drives the gate of an external N-channel MOSFET for linear regulator.jxh嘉泰姆

12jxh嘉泰姆

10jxh嘉泰姆

FB3jxh嘉泰姆

These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components.jxh嘉泰姆

13jxh嘉泰姆

11jxh嘉泰姆

FS/SYNCjxh嘉泰姆

This pin is used to adjust the switching frequency. Connecting a resistor from FS/SYNC pin to the ground increases the switching frequency. Conversely,connecting a resistor from this pin to the VCC12 reduces the switching frequency. In addition, this pin also provides synchronous frequency function. An external clock can be fed into this pin, and force the switching frequency to follow the external clock.jxh嘉泰姆

14jxh嘉泰姆

12jxh嘉泰姆

PGOODjxh嘉泰姆

This pin is an open drain device; connect a pull up resistor to the VCC for PGOOD function.jxh嘉泰姆

15jxh嘉泰姆

13jxh嘉泰姆

GNDjxh嘉泰姆

This pin is the signal ground pin. The metal thermal pad under the package is the IC substrate; connects the GND pin and metal thermal pad together on the board, and ties to the good GND plane for electrical and thermal conduction.jxh嘉泰姆

16jxh嘉泰姆

16jxh嘉泰姆

BOOT2jxh嘉泰姆

These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. It can be connected to a power voltage directly, but the difference voltage between the BOOT and VIN must be high enough to drive the upper MOSFETs.jxh嘉泰姆

17jxh嘉泰姆

14jxh嘉泰姆

UGATE2jxh嘉泰姆

These pins provide the gate driver for the upper MOSFETs of VOUT1 and VOUT2.jxh嘉泰姆

18jxh嘉泰姆

18,23jxh嘉泰姆

PGNDjxh嘉泰姆

This pin is the power ground pin for the gate driver and linear driver circuit. It should be tied to the GND.jxh嘉泰姆

19jxh嘉泰姆

20jxh嘉泰姆

LGATE2jxh嘉泰姆

These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2.jxh嘉泰姆

20jxh嘉泰姆

21jxh嘉泰姆

LGATE1jxh嘉泰姆

These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2.jxh嘉泰姆

21jxh嘉泰姆

19, 22jxh嘉泰姆

VCC12jxh嘉泰姆

Power supply input pin. Connect a nominal 12V power supply to this pin for the gate driver. It is recommended that a decoupling capacitor (1 to 10μF) is connected to the GND for noise decoupling.jxh嘉泰姆

六.电路原理图jxh嘉泰姆


blob.pngjxh嘉泰姆

七,功能概述jxh嘉泰姆


Soft-Start/Enablejxh嘉泰姆
The three SS/EN pins control the soft-start and enable or disable the controller. In Independent mode, the threejxh嘉泰姆
regulators all have independent soft-start and enable functions. Connect a soft-start capacitor from each SS/ENjxh嘉泰姆
pin to the GND to set the soft-start interval, and an open drain logic signal for each SS/EN pin will enable or dis-jxh嘉泰姆
able the respective output.jxh嘉泰姆

八,相关产品            更多同类产品......  jxh嘉泰姆


Switching Regulator >   Buck Controllerjxh嘉泰姆

Part_No jxh嘉泰姆

Package jxh嘉泰姆

Archijxh嘉泰姆

tectujxh嘉泰姆

Phasejxh嘉泰姆

No.ofjxh嘉泰姆

PWMjxh嘉泰姆

Outputjxh嘉泰姆

Output jxh嘉泰姆

Currentjxh嘉泰姆

(A) jxh嘉泰姆

Inputjxh嘉泰姆

Voltage (V) jxh嘉泰姆

Referencejxh嘉泰姆

Voltagejxh嘉泰姆

(V) jxh嘉泰姆

Bias jxh嘉泰姆

Voltagejxh嘉泰姆

(V) jxh嘉泰姆

Quiescentjxh嘉泰姆

Currentjxh嘉泰姆

(uA) jxh嘉泰姆

minjxh嘉泰姆

maxjxh嘉泰姆

CXSD6273jxh嘉泰姆

SOP-14jxh嘉泰姆

QSOP-16jxh嘉泰姆

QFN4x4-16jxh嘉泰姆

VM    jxh嘉泰姆

1   jxh嘉泰姆

1     jxh嘉泰姆

30jxh嘉泰姆

2.9    jxh嘉泰姆

13.2jxh嘉泰姆

0.9jxh嘉泰姆

12     jxh嘉泰姆

8000jxh嘉泰姆

CXSD6274jxh嘉泰姆

SOP-8jxh嘉泰姆

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1jxh嘉泰姆

1jxh嘉泰姆

20jxh嘉泰姆

2.9  jxh嘉泰姆

13.2 jxh嘉泰姆

0.8jxh嘉泰姆

12jxh嘉泰姆

5000jxh嘉泰姆

CXSD6274Cjxh嘉泰姆

SOP-8jxh嘉泰姆

VMjxh嘉泰姆

1jxh嘉泰姆

1jxh嘉泰姆

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13.2jxh嘉泰姆

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5000jxh嘉泰姆

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QFN4x4-24jxh嘉泰姆

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1jxh嘉泰姆

60jxh嘉泰姆

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5000jxh嘉泰姆

CXSD6276jxh嘉泰姆

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1jxh嘉泰姆

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20jxh嘉泰姆

2.2jxh嘉泰姆

13.2jxh嘉泰姆

0.8jxh嘉泰姆

5~12jxh嘉泰姆

2100jxh嘉泰姆

CXSD6276Ajxh嘉泰姆

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VMjxh嘉泰姆

1jxh嘉泰姆

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20jxh嘉泰姆

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13.2jxh嘉泰姆

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2100jxh嘉泰姆

CXSD6277/A/Bjxh嘉泰姆

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1jxh嘉泰姆

1jxh嘉泰姆

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1.25|0.8jxh嘉泰姆

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3000jxh嘉泰姆

CXSD6278jxh嘉泰姆

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2100jxh嘉泰姆

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1jxh嘉泰姆

1jxh嘉泰姆

10jxh嘉泰姆

5jxh嘉泰姆

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2000jxh嘉泰姆

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