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CXSD6279B电压模式和同步PWM控制器驱动双N通道mosfet控制监视和保护功能受控电源带欠压和过流保护的输出
发表时间:2020-04-21浏览次数:126
CXSD6279B电压模式和同步PWM控制器驱动双N通道mosfet控制监视和保护功能受控电源带欠压和过流保护的输出
 

目录pA3嘉泰姆

1.产品概述                       2.产品特点pA3嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 pA3嘉泰姆
5.产品封装图                     6.电路原理图                   pA3嘉泰姆
7.功能概述                        8.相关产品pA3嘉泰姆

一,产品概述(General Description)      pA3嘉泰姆


                The CXSD6279B is a voltage mode and synchronous PWM controllerpA3嘉泰姆
which drives dual N-Channel MOSFETs. It inte-grates the control, monitoring,pA3嘉泰姆
and protection functions into a single package, provides one controlled powerpA3嘉泰姆
outputs with under-voltage and over-current protection.CXSD6279B providespA3嘉泰姆
excellent regulation for output load variation. An internal 0.8V temperature-pA3嘉泰姆
compensated reference voltage is designed to meet the requirement ofpA3嘉泰姆
low output voltage applications. It includes a 200kHz free-runningpA3嘉泰姆
triangle-wave oscillator that is adjustable from 70kHz to 800kHz.pA3嘉泰姆
        The power-on-reset (POR) circuit monitors the VCC, EN,and OCSETpA3嘉泰姆
input voltage to start-up or shutdown the IC.The over-current protection (OCP)pA3嘉泰姆
monitors the output current by using the voltage drop across the upperpA3嘉泰姆
MOSFET’s RDS(ON), eliminating the need for a current sens-ing resistor.pA3嘉泰姆
The under-voltage protection (UVP) moni-tors the voltage of the FB pin forpA3嘉泰姆
short-circuit protection.The over-current protection trip cycle the soft-startpA3嘉泰姆
func-tion until the fault events be removed. Under-voltage pro-tection willpA3嘉泰姆
shutdown the IC directly.pA3嘉泰姆
二.产品特点(Features)pA3嘉泰姆


1.)Simple Single-Loop Control DesignpA3嘉泰姆
   Voltage-Mode PWM ControlpA3嘉泰姆
2.)Fast Transient ResponsepA3嘉泰姆
    Full 0–100% Duty RatiopA3嘉泰姆
3.)Excellent Output Voltage RegulationpA3嘉泰姆
   0.8V Internal ReferencepA3嘉泰姆
    ± 1% Over Line Voltage and TemperaturepA3嘉泰姆
4.)Over Current Fault MonitorpA3嘉泰姆
   Uses Upper MOSFETs RDS (ON)pA3嘉泰姆
5.)Converter Can Source and Sink CurrentpA3嘉泰姆
6.)Small Converter SizepA3嘉泰姆
    200kHz Free-Running OscillatorpA3嘉泰姆
   Programmable from 70kHz to 800kHzpA3嘉泰姆
7.)14-Lead SOIC PackagepA3嘉泰姆
8.)Lead Free and Green Devices Available (RoHS Compliant)pA3嘉泰姆
三,应用范围 (Applications)pA3嘉泰姆


Graphic CardspA3嘉泰姆
DDR Memory Power SupplypA3嘉泰姆
DDR Memory Termination VoltagepA3嘉泰姆
Low-Voltage Distributed Power SuppliespA3嘉泰姆
四.下载产品资料PDF文档 pA3嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持pA3嘉泰姆

 QQ截图20160419174301.jpgpA3嘉泰姆

五,产品封装图 (Package)pA3嘉泰姆


pA3嘉泰姆
RT (Pin1)pA3嘉泰姆
This pin can adjust the switching frequency. Connect a resistor from the RT to the GND for increasing the switch-pA3嘉泰姆
OCSET (Pin2)pA3嘉泰姆
This pin serves two functions: a shutdown control and the setting of over current-limit threshold. Pulling this pinpA3嘉泰姆
below 1.27V will shutdown the controller, forcing the UGATE and LGATE signals to be at 0V.pA3嘉泰姆
A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over pA3嘉泰姆

current limit. An internal 200μA current source will flow through this resistor, creating a voltage drop, which pA3嘉泰姆

will be com-pared with the voltage across the high side MOSFET.pA3嘉泰姆
SS (Pin3)pA3嘉泰姆
Connect a capacitor from the pin to the GND to set the soft-start interval of the converter. An internal 10μA pA3嘉泰姆

current source charges this capacitor to 5.8V. The SS voltage clamps the error amplifier output, and Figure1pA3嘉泰姆

 shows the soft-start interval. At t1, the SS voltage reaches the valley of the oscillator’s triangle wave. ThepA3嘉泰姆

PWM comparator starts to generate a PWM signal to control logic, and thepA3嘉泰姆
COMP (Pin4)pA3嘉泰姆
This pin is the output of the error amplifier. Add an exter-nal resistor and capacitor network to provide thepA3嘉泰姆

 loop com- pensation for the PW M converter (see Application Information).pA3嘉泰姆
FB (Pin5)pA3嘉泰姆
FB pin is the inverter input of the error amplifier and it receives the feedback voltage from an external pA3嘉泰姆

resis-tive divider across the output (V OUT). The output voltage is determined by:pA3嘉泰姆
EN (Pin6)pA3嘉泰姆
Pull the pin higher than 2V to enable the device, and pull the pin lower than 0.8V to shutdown the pA3嘉泰姆

device. In shutdown, the SS is discharged and the UGATE and LGATE pins are held low. The EN pin pA3嘉泰姆

is the open-collector, and it will not be floating. pA3嘉泰姆
GND (Pin7)pA3嘉泰姆
Signal ground for the IC. pA3嘉泰姆
PHASE (Pin8)pA3嘉泰姆
This pin is connected to the source of the high-side MOSFET and is used to monitor the voltage droppA3嘉泰姆

 across the high-side MOSFET for over-current protection. pA3嘉泰姆
UGATE (Pin9)pA3嘉泰姆
Connect the pin to external MOSFET, and provides the gate drive for the upper MOSFET.pA3嘉泰姆

BOOT (Pin 10)pA3嘉泰姆
This pin provides the supply voltage to the high side MOSFET driver. For driving logic level N-channel pA3嘉泰姆

MOSEFT,a bootstrap circuit can be used to create a suitable driver’s supply. pA3嘉泰姆
PGND (Pin11)pA3嘉泰姆
Power ground for the gate diver. Connect the lower MOSFET source to this pin. pA3嘉泰姆
LGATE (Pin 12)pA3嘉泰姆

Connect the pin to the external MOSFET, and provides the gate drive signal for the lower MOSFET.pA3嘉泰姆
PVCC (Pin13)pA3嘉泰姆
This pin provides a supply voltage for the lower gate drive, connect it to the VCC pin in common use. pA3嘉泰姆
VCC (Pin14)pA3嘉泰姆
This pin provides a supply voltage for the device. When the VCC is above the rising threshold 10.4V, pA3嘉泰姆

the device is turned on; conversely, when the VCC is below the falling threshold, the device is turned off.pA3嘉泰姆
六.电路原理图pA3嘉泰姆


blob.pngpA3嘉泰姆
七,功能概述pA3嘉泰姆


Output Capacitor SelectionpA3嘉泰姆
The selection of COUT is determined by the required effec-tive series resistance (ESR) and voltage ratingpA3嘉泰姆

 rather than the actual capacitance requirement. Therefore, select highperformance low ESR capacitors pA3嘉泰姆

that are intended for switching regulator applications. In some applications,multiple capacitors have topA3嘉泰姆

 be paralled to achieve the desired ESR value. If tantalum capacitors are used, makesure they are surgepA3嘉泰姆

 tested by the manufactures. If in doubt,consult the capacitors manufacturer.pA3嘉泰姆
 Input Capacitor SelectionpA3嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable pA3嘉泰姆

operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum inputpA3嘉泰姆

 voltage. The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the pA3嘉泰姆

load current. During power up, the input capaci-tors have to handle large amount of surge current.pA3嘉泰姆

 If tanta-lum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, pA3嘉泰姆

consult the capacitors manufacturer.For high frequency decoupling, a ceramic capacitor be-tweenpA3嘉泰姆

 0.1μF to 1μF can be connected between the VCC and the ground pin.pA3嘉泰姆
Inductor SelectionpA3嘉泰姆
The inductance of the inductor is determined by the out-put voltage requirement. The larger the pA3嘉泰姆

inductance, the lower the inductor’s current ripple. This will translate into lower output ripple voltage.pA3嘉泰姆

 The ripple current and ripple voltage can be approximated by:pA3嘉泰姆
where Fs is the switching frequency of the regulator.There is a tradeoff exists between the inductor’spA3嘉泰姆

 ripple current and the regulator load transient response time. A smaller inductor will give the regulator pA3嘉泰姆

a faster load tran-sient response at the expense of higher ripple current and vice versa. The maximumpA3嘉泰姆

 ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple pA3嘉泰姆

current to be approximately 30% of the maxi-mum output current.Once the inductance value has pA3嘉泰姆

been chosen, select an inductor that is capable of carrying the required peak cur-rent without going pA3嘉泰姆

into saturation. In some types of inductors, especially core that is make of ferrite, the ripplepA3嘉泰姆
current will increase abruptly when it saturates. This will result in a larger output ripple voltage.pA3嘉泰姆
CompensationpA3嘉泰姆
The output LC filter introduces a double pole, which con-tributes with –40dB/decade gain slope and pA3嘉泰姆

180 degrees phase shift in the control loop. A compensation network between the COMP pin and the pA3嘉泰姆

ground should be added. The simplest loop compensation network is shown inpA3嘉泰姆
Figure 5.pA3嘉泰姆
The output LC filter consists of the output inductor and output capacitors. The transfer function ofpA3嘉泰姆

 the LC filter is given by:pA3嘉泰姆
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