• "

产品订购

目录P0j嘉泰姆

1.产品概述                       2.产品特点P0j嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 P0j嘉泰姆
5.产品封装图                     6.电路原理图                   P0j嘉泰姆
7.功能概述                        8.相关产品P0j嘉泰姆

一,产品概述(General Description)  P0j嘉泰姆

    The CXSD62121A CXSD62121B CXSD62121 integrates a synchronous buck PWM con-troller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It offers the lowest total solution cost in system where space is at a premium.  The CXSD62121A CXSD62121B CXSD62121 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), the CXSD62121A CXSD62121B CXSD62121 provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. On TQFN-20 Package,the Forced PWM Mode works nearly at constant frequency for low-noise requirements.  The CXSD62121A CXSD62121B CXSD62121 is equipped with accurate current-limit,output under-voltage, and output over-voltage protections.A Power-On- Reset function monitors the voltage on VCC prevents wrong operation during power on. Droop func-tion is allowed to adjust output voltage during light load period.The LDO is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination.The device integrates two power transistors to source or sink current up to 1.5A. It also incorporates current-limit and thermal shutdown protection.The output voltage of LDO tracks the voltage at VREF pin.An internal resistor divider is used to provide a half volt-age of VREF for VTTREF and VTT Voltage. The VTT output voltage is only requiring 20μF of ceramic output capaci tance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state)and suspend state (S4/S5 state) for device, when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF                                                         P0j嘉泰姆

产品特点(Features)P0j嘉泰姆

High Input Voltages Range from 3V to 28V Input PowerP0j嘉泰姆
Provide Adjustable Output Voltage from 0.75V toP0j嘉泰姆
5.5V +1% Accuracy over TemperatureP0j嘉泰姆
Integrated MOSFET Drivers and Bootstrap Forward P-CH MOSFETP0j嘉泰姆
Low Quiescent Current (200μA)P0j嘉泰姆
Excellent Line and Load Transient ResponsesP0j嘉泰姆
PFM Mode for Increased Light Load EfficiencyP0j嘉泰姆
Constant On-Time Controller SchemeP0j嘉泰姆
- Switching Frequency Compensation for PWM ModeP0j嘉泰姆
- Adjustable Switching Frequency from 100kHz toP0j嘉泰姆
550kHz in PWM Mode with DC Output CurrentP0j嘉泰姆
S3 and S5 Pins Control The Device in S0, S3 or S4/S5 StateP0j嘉泰姆
Power Good MonitoringP0j嘉泰姆
Extra Droop Voltage Control Function withP0j嘉泰姆
Adjustable Current SettingP0j嘉泰姆
70% Under-Voltage Protection (UVP)P0j嘉泰姆
125% Over-Voltage Protection (OVP)P0j嘉泰姆
Adjustable Current-Limit ProtectionP0j嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)P0j嘉泰姆
TQFN-20 3mmx3mm Thin packageP0j嘉泰姆
Lead Free Available (RoHS Compliant)P0j嘉泰姆
+1.5A LDO Section (VTT)P0j嘉泰姆
Sourcing or Sinking Current up to 1.5AP0j嘉泰姆
Fast Transient Response for Output VoltageP0j嘉泰姆
Output Ceramic Capacitors Support at least 10μF MLCCP0j嘉泰姆
VTT and VTTREF Track at Half the VDDQSNS by internal dividerP0j嘉泰姆
+20mV Accuracy for VTT and VTTREFP0j嘉泰姆
Independent Over-Current Limit (OCL)P0j嘉泰姆
Thermal Shutdown ProtectionP0j嘉泰姆
三,应用范围 (Applications)P0j嘉泰姆

DDR2, and DDR3 Memory Power SuppliesP0j嘉泰姆
SSTL-2 SSTL-18 and HSTL TerminationP0j嘉泰姆
四.下载产品资料PDF文档 P0j嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！P0j嘉泰姆

 P0j嘉泰姆

五,产品封装图 (Package)P0j嘉泰姆

P0j嘉泰姆
六.电路原理图P0j嘉泰姆

P0j嘉泰姆

七,功能概述P0j嘉泰姆

Soft- Start (cont.)P0j嘉泰姆

During soft-start stage before the PGOOD pin is ready,P0j嘉泰姆
the under voltage protection is prohibited. The over volt-P0j嘉泰姆
age and current limit protection functions are enabled. IfP0j嘉泰姆
the output capacitor has residue voltage before startup,P0j嘉泰姆
both low-side and high-side MOSFETs are in off-stateP0j嘉泰姆
until the internal digital soft start voltage equal the inter-P0j嘉泰姆
nal feedback voltage. This will ensure the output voltageP0j嘉泰姆
starts from its existing voltage level.P0j嘉泰姆
The VTT LDO part monitors the output current, both sourc-P0j嘉泰姆
ing and sinking current, and limits the maximum outputP0j嘉泰姆
current to prevent damages during current overload orP0j嘉泰姆
short circuit (shorted from VTT to GND or VLDOIN)P0j嘉泰姆
conditions.P0j嘉泰姆
The VTT LDO provides a soft-start function, using theP0j嘉泰姆
constant current to charge the output capacitor that givesP0j嘉泰姆
a rapid and linear output voltage rise. If the load current isP0j嘉泰姆
above the current limit start-up, the VTT cannot startP0j嘉泰姆
successfully.CXSD62121A CXSD62121B CXSD62121 has an independent counter for each output,P0j嘉泰姆
but the PGOOD signal indicates only the status of VDDQP0j嘉泰姆
and does not indicate VTT power good externally.P0j嘉泰姆
Power-Good Output (PGOOD)P0j嘉泰姆
PGOOD is an open-drain output and the PGOOD com-P0j嘉泰姆
parator continuously monitors the output voltage. PGOODP0j嘉泰姆
is actively held low in shutdown, and standby. When PWMP0j嘉泰姆
converter’s output voltage is greater than 95% of its tar-P0j嘉泰姆
get value, the internal open-drain device will be pulledP0j嘉泰姆
low. After 63μs debounce time, the PGOOD goes high.P0j嘉泰姆
The PGOOD goes low if VVDDQ output is 10% below orP0j嘉泰姆
above its nominal regulation point.P0j嘉泰姆
Under Voltage ProtectionP0j嘉泰姆
In the process of operation, if a short-circuit occurs, theP0j嘉泰姆
output voltage will drop quickly. When load current is big-P0j嘉泰姆
ger than current limit threshold value, the output voltageP0j嘉泰姆
will fall out of the required regulation range. The under-P0j嘉泰姆
voltage continually monitors the setting output voltageP0j嘉泰姆
after 2ms of PWM operations to ensure startup. If a loadP0j嘉泰姆
step is strong enough to pull the output voltage lowerP0j嘉泰姆
than the under voltage threshold (70% of normal outputP0j嘉泰姆
voltage), CXSD62121A CXSD62121B CXSD62121 shuts down the output gradually andP0j嘉泰姆
latches off both high and low side MOSFETs.P0j嘉泰姆
Over Voltage Protection (OVP)P0j嘉泰姆
The feedback voltage should increase over 125% of theP0j嘉泰姆
reference voltage due to the high-side MOSFET failure orP0j嘉泰姆
for other reasons, and the over voltage protection com-P0j嘉泰姆
parator designed with a 1.5μs noise filter will force theP0j嘉泰姆
low-side MOSFET gate driver to be high. This action ac-P0j嘉泰姆
tively pulls down the output voltage and eventually at-P0j嘉泰姆
tempts to blow the battery fuse.P0j嘉泰姆
When the OVP occurs, the PGOOD pin will pull down andP0j嘉泰姆
latch-off the converter. This OVP scheme only clamps theP0j嘉泰姆
voltage overshoot, and does not invert the output voltageP0j嘉泰姆
when otherwise activated with a continuously high outputP0j嘉泰姆
from low-side MOSFET driver. It’s a common problem forP0j嘉泰姆
OVP schemes with a latch. Once an over-voltage faultP0j嘉泰姆
condition is set, toggling VCC power-on-reset signal canP0j嘉泰姆
only reset it.P0j嘉泰姆
PWM Converter Current LimitP0j嘉泰姆
The current-limit circuit employs a unique “valley” currentP0j嘉泰姆
sensing algorithm (Figure 2). CS pin should be con-P0j嘉泰姆
nected to VCC through the trip voltage-setting resistor,P0j嘉泰姆
RCS. CS terminal sinks 5mA current, ICS, and the currentP0j嘉泰姆
limit threshold is set to the voltage across the RCS. TheP0j嘉泰姆
voltage between or CS_GND pin and PHASE pin moni-P0j嘉泰姆
tors the inductor current so that PHASE pin should beP0j嘉泰姆
connected to the drain terminal of the low side MOSFET.P0j嘉泰姆
PGND is used as the positive current sensing node soP0j嘉泰姆
that PGND should be connected to the proper currentP0j嘉泰姆
sensing device, i.e. the sense resistor or the source ter-P0j嘉泰姆
minal of the low side MOSFET.P0j嘉泰姆
If the magnitude of the current-sense signal is above theP0j嘉泰姆
current-limit threshold, the PWM is not allowed to initiateP0j嘉泰姆
a new cycle. The actual peak current is greater than theP0j嘉泰姆
current-limit threshold by an amount equal to the induc-P0j嘉泰姆
tor ripple current. Therefore, the exact current- limit char-P0j嘉泰姆
acteristic and maximum load capability are a function ofP0j嘉泰姆
the sense resistance, inductor value, and input voltage.P0j嘉泰姆
八,相关产品               更多同类产品...... P0j嘉泰姆

 P0j嘉泰姆

◀ 上一篇:CXSD62121B功率因数调制（PFM）或脉冲宽度调制（PWM）模式下提供出色的瞬态响应和准确的直流电压输出

返回顶部

下一篇▶:5A同步降压转换器CXSD62122 50mΩ P沟道功率MOSFET和20mΩ N沟道功率MOSFET电流模式控制方案