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目录1Ug嘉泰姆

1.产品概述                       2.产品特点1Ug嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 1Ug嘉泰姆
5.产品封装图                     6.电路原理图                   1Ug嘉泰姆
7.功能概述                        8.相关产品1Ug嘉泰姆

一,产品概述(General Description)   1Ug嘉泰姆

  The CXSD62118 is a single-phase, constant-on-time,synchronous PWM controller, which drives N-channel MOSFETs. The CXSD62118 steps down high voltage to generate low-voltage chipset or RAM supplies in notebook computers.1Ug嘉泰姆
  The CXSD62118 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), the CXSD62118 provides very high efficiency over light to heavy loads with loading-1Ug嘉泰姆
modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements.1Ug嘉泰姆
  The CXSD62118 is equipped with accurate positive current-limit, output under-voltage, and output over-voltage protections, perfect for NB applications. The Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The CXSD62118 has a 1ms digital soft-start and built-in an integrated output discharge method for soft-stop. An internal integrated1Ug嘉泰姆
soft-start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors with controlled reverse inductor current.1Ug嘉泰姆
  The CXSD62118 is available in 10pin TDFN 3x3 package.1Ug嘉泰姆
二.产品特点(Features)1Ug嘉泰姆

Adjustable Output Voltage from +0.7V to +5.5V1Ug嘉泰姆
- 0.7V Reference Voltage1Ug嘉泰姆
- ±1% Accuracy Over-Temperature1Ug嘉泰姆
Operates from an Input Battery Voltage Range of1Ug嘉泰姆
+1.8V to +28V1Ug嘉泰姆
Power-On-Reset Monitoring on VCC Pin1Ug嘉泰姆
Excellent Line and Load Transient Responses1Ug嘉泰姆
PFM Mode for Increased Light Load Efficiency1Ug嘉泰姆
Selectable PWM Frequency from 4 Preset Values1Ug嘉泰姆
Integrated MOSFET Drivers1Ug嘉泰姆
Integrated Bootstrap Forward P-CH MOSFET1Ug嘉泰姆
Adjustable Integrated Soft-Start and Soft-Stop1Ug嘉泰姆
Selectable Forced PWM or Automatic PFM/PWM Mode1Ug嘉泰姆
Power Good Monitoring1Ug嘉泰姆
70% Under-Voltage Protection1Ug嘉泰姆
125% Over-Voltage Protection1Ug嘉泰姆
Adjustable Current-Limit Protection1Ug嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)1Ug嘉泰姆
Over-Temperature Protection1Ug嘉泰姆
TDFN-10 3x3 Package1Ug嘉泰姆
Lead Free and Green Devices Available1Ug嘉泰姆
三,应用范围 (Applications)1Ug嘉泰姆

Notebook1Ug嘉泰姆
Table PC1Ug嘉泰姆
Hand-Held Portable1Ug嘉泰姆
AIO PC1Ug嘉泰姆
四.下载产品资料PDF文档 1Ug嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！1Ug嘉泰姆

 1Ug嘉泰姆

五,产品封装图 (Package)1Ug嘉泰姆

1Ug嘉泰姆

六.电路原理图1Ug嘉泰姆

1Ug嘉泰姆

七,功能概述1Ug嘉泰姆

Input Capacitor Selection (Cont.)1Ug嘉泰姆
higher than the maximum input voltage. The maximum RMS current rating requirement is approximately1Ug嘉泰姆

 IOUT/2,where IOUT is the load current. During power-up, the input capacitors have to handle great 1Ug嘉泰姆

amount of surge current.For low-duty notebook appliactions, ceramic capacitor is recommended. The1Ug嘉泰姆

 capacitors must be connected be-tween the drain of high-side MOSFET and the source of low-side 1Ug嘉泰姆

MOSFET with very low-impeadance PCB layout1Ug嘉泰姆
MOSFET Selection1Ug嘉泰姆
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs1Ug嘉泰姆

 should be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:1Ug嘉泰姆
For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET1Ug嘉泰姆

 driver will not charge the miller capacitor of this MOSFET.In the turning off process of the low-side MOSFET,1Ug嘉泰姆

 the load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the 1Ug嘉泰姆

miller capaci-tor through the low-side MOSFET driver sinking current path. This results in much less switching1Ug嘉泰姆

 loss of the low-side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the 1Ug嘉泰姆

low-side MOSFET will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con-verter can reduce power loss. The gate charge for this MOSFET is usually the 1Ug嘉泰姆

secondary consideration. The high-side MOSFET does not have this zero voltage switch- ing condition;1Ug嘉泰姆

 in addition, because  it conducts for less time compared to the low-side MOSFET, the switching 1Ug嘉泰姆

loss tends to be dominant. Priority  should be given to the MOSFETs with less gate charge, so 1Ug嘉泰姆

that both the gate driver loss and switching loss  will be minimized.1Ug嘉泰姆

The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing1Ug嘉泰姆

 transfer capaci-tance (CRSS) and maximum output current requirement. The losses in the 1Ug嘉泰姆

MOSFETs have two components:conduction loss and transition loss. For the high-side and 1Ug嘉泰姆

low-side MOSFETs, the losses are approximately given by the following equations:1Ug嘉泰姆

Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW1Ug嘉泰姆
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)1Ug嘉泰姆
Where I is the load current OUT1Ug嘉泰姆
TC is the temperature dependency of RDS(ON)1Ug嘉泰姆
FSW is the switching frequency1Ug嘉泰姆
tSW is the switching interval1Ug嘉泰姆
D is the duty cycle1Ug嘉泰姆
Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional 1Ug嘉泰姆

transition loss.The switching interval, tSW, is the function of the reverse transfer capacitance CRSS. 1Ug嘉泰姆

The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted 1Ug嘉泰姆

from the “RDS(ON) vs. Temperature” curve of the power MOSFET.1Ug嘉泰姆
Layout Consideration1Ug嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation 1Ug嘉泰姆

of the regulator.With power devices switching at higher frequency, the resulting current transient will 1Ug嘉泰姆

cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example,1Ug嘉泰姆

 consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying1Ug嘉泰姆

 the full load current. During turn-off,current stops flowing in the MOSFET and is freewheeling by the 1Ug嘉泰姆

low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage 1Ug嘉泰姆

spike during the switching interval. In general, using short and wide printed circuit traces should1Ug嘉泰姆

 minimize interconnect-ing impedances and the magnitude of voltage spike.1Ug嘉泰姆
Besides, signal and power grounds are to be kept sepa-rating and finally combined using ground 1Ug嘉泰姆

plane construc-tion or single point grounding. The best tie-point between the signal ground and the 1Ug嘉泰姆

power ground is at the nega-tive side of the output capacitor on each channel, where there is less 1Ug嘉泰姆

noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout:1Ug嘉泰姆
· Keep the switching nodes (UGATE, LGATE, BOOT,and PHASE) away from sensitive small signal 1Ug嘉泰姆

nodes since these nodes are fast moving signals.Therefore, keep traces to these nodes as short as1Ug嘉泰姆
possible and there should be no other weak signal traces in parallel with theses traces on any layer.1Ug嘉泰姆

Layout Consideration (Cont.)1Ug嘉泰姆
· The signals going through theses traces have both high dv/dt and high di/dt with high peak 1Ug嘉泰姆

charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and 1Ug嘉泰姆

LGATE) should be short and wide.1Ug嘉泰姆
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as 1Ug嘉泰姆

possible.Minimizing the impedance with wide layout plane be-tween the two pads reduces the 1Ug嘉泰姆

voltage bounce of the node. In addition, the large layout plane between the drain of the 1Ug嘉泰姆

MOSFETs (VIN and PHASE nodes) can get better heat sinking.1Ug嘉泰姆

The GND is the current sensing circuit reference ground and also the power ground of the 1Ug嘉泰姆

LGATE low-side MOSFET. On the other hand, the GND trace should be a separate trace and1Ug嘉泰姆

 independently go to the source of the low-side MOSFET. Besides, the cur-rent sense resistor 1Ug嘉泰姆

should be close to OCSET pin to avoid parasitic capacitor effect and noise coupling.1Ug嘉泰姆

· Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. 1Ug嘉泰姆

(For example,place the decoupling ceramic capacitor close to the drain of the high-side MOSFET1Ug嘉泰姆

 as close as possible.)1Ug嘉泰姆
· The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output1Ug嘉泰姆

 bulk capaci-tors should be close to the loads. The input capaci-tor’s ground should be close to the1Ug嘉泰姆

 grounds of the output capacitors and low-side MOSFET.1Ug嘉泰姆
· Locate the resistor-divider close to the FB pin to mini-mize the high impedance trace. In addition, 1Ug嘉泰姆

FB pin traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE).1Ug嘉泰姆

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