目录0Zw嘉泰姆

1.产品概述                       2.产品特点0Zw嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 0Zw嘉泰姆
5.产品封装图                     6.电路原理图                   0Zw嘉泰姆
7.功能概述                        8.相关产品0Zw嘉泰姆

一,产品概述(General Description)    0Zw嘉泰姆

          The CXSD62126 is a 3A synchronous-rectified Buck converter with integrated0Zw嘉泰姆
70m Ω power MOSFETs. The CXSD62126, designed with a current-mode control0Zw嘉泰姆
scheme,can convert wide input voltage of 4.3V to 14V to the output voltage0Zw嘉泰姆
adjustable from 0.8V to VIN to provide excellent output voltage regulation.0Zw嘉泰姆
For high efficiency over all load current range, the CXSD62126 is equipped0Zw嘉泰姆
with an automatic Skip/PWM mode operation. At light load, the IC operates0Zw嘉泰姆
in the Skip mode, which keeps a constant minimum inductor peak current,0Zw嘉泰姆
to reduce switching losses. At heavy load, the IC works in PWM mode, which0Zw嘉泰姆
inductor peak current is programmed by the COMP voltage, to provide high0Zw嘉泰姆
efficiency and excel lent output voltage regulation.The CXSD62126 is also0Zw嘉泰姆
equipped with power-on-reset,soft-start, soft-stop, and whole protections0Zw嘉泰姆
(under-voltage,over-voltage, over-temperature, and current-limit) into a0Zw嘉泰姆
single package. In shutdown mode, the supply current drops below 3μA.0Zw嘉泰姆
This device, available in a 8-pin SOP-8 package, provides a very compact0Zw嘉泰姆
system solution with minimal external components and PCB area.0Zw嘉泰姆
二.产品特点(Features)0Zw嘉泰姆

Wide Input Voltage from 4.3V to 14V0Zw嘉泰姆
Output Current up to 3A0Zw嘉泰姆
Adjustable Output Voltage from 0.8V to V IN0Zw嘉泰姆
- ±2% System Accuracy0Zw嘉泰姆
70mΩ Integrated Power MOSFETs0Zw嘉泰姆
High Efficiency up to 95%0Zw嘉泰姆
- Automatic Skip/PWM Mode Operation0Zw嘉泰姆
Current-Mode Operation0Zw嘉泰姆
- Easy Feedback Compensation0Zw嘉泰姆
- Stable with Low ESR Output Capacitors0Zw嘉泰姆
- Fast Load/Line Transient Response0Zw嘉泰姆
Power-On-Reset Monitoring0Zw嘉泰姆
Fixed 500kHz Switching Frequency in PWM Mode0Zw嘉泰姆
Built-In Digital Soft-Start and Soft-Stop0Zw嘉泰姆
Current-Limit Protection with Frequency Foldback0Zw嘉泰姆
123% Over-Voltage Protection0Zw嘉泰姆
Hiccup-Mode 50% Under-Voltage Protection0Zw嘉泰姆
Over-Temperature Protection0Zw嘉泰姆
<3μA Quiescent Current in Shutdown Mode0Zw嘉泰姆
Small SOP-8 Package0Zw嘉泰姆
Lead Free and Green Devices Available0Zw嘉泰姆
(RoHS Compliant)0Zw嘉泰姆
三,应用范围 (Applications)0Zw嘉泰姆

OLPC, UMPC0Zw嘉泰姆
Notebook Computer0Zw嘉泰姆
Handheld Portable Device0Zw嘉泰姆
Step-Down Converters Requiring High Efficiency0Zw嘉泰姆
and 3A Output Current0Zw嘉泰姆
四.下载产品资料PDF文档 0Zw嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！0Zw嘉泰姆

 0Zw嘉泰姆

五,产品封装图 (Package)0Zw嘉泰姆

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六.电路原理图0Zw嘉泰姆

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七,功能概述0Zw嘉泰姆

Thermal Consideration0Zw嘉泰姆

In most applications, the JTMA7104A does not dissipate much heat due to its high efficiency. But, in applications0Zw嘉泰姆
where the JTMA7104A is running at high ambient tem perature with low supply voltage and high duty cycles, the0Zw嘉泰姆
heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches0Zw嘉泰姆
approximately 150°C, both power switches will be turned off and the SW node will become high impedance.0Zw嘉泰姆
To avoid the JTMA7104A from exceeding the maximum junction temperature, the user will need to do some ther-0Zw嘉泰姆
mal analysis. The goal of the thermal analysis is to deter mine whether the power dissipated exceeds the maxi-0Zw嘉泰姆
mum junction temperature of the part. The power dissipated by the part is approximated:0Zw嘉泰姆
PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D))0Zw嘉泰姆
The temperature rise is given by:0Zw嘉泰姆
TR = (PD)(èJA)0Zw嘉泰姆
Where PD is the power dissipated by the regulator, D is0Zw嘉泰姆
duty cycle of main switch0Zw嘉泰姆
D = VOUT/VIN0Zw嘉泰姆
The èJA is the thermal resistance from the junction of the0Zw嘉泰姆
die to the ambient temperature. The junction temperature,0Zw嘉泰姆
TJ, is given by:0Zw嘉泰姆
TJ = TA + TR0Zw嘉泰姆
Where TA is the ambient temperature.
Layout Consideration0Zw嘉泰姆
For all switching power supplies, the layout is an impor tant step in the design; especially at high peak currents0Zw嘉泰姆
and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty0Zw嘉泰姆
cycle jitter.0Zw嘉泰姆
1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with0Zw嘉泰姆
short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND0Zw嘉泰姆
to capacitor less than 2mm respectively is recommended.0Zw嘉泰姆
2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed0Zw嘉泰姆
as close as possible to the SW pin to minimize the noise coupling into other circuits.0Zw嘉泰姆
3. The output capacitor should be place closed to converter VOUT and GND.0Zw嘉泰姆
4. Since the feedback pin and network is a high imped ance circuit the feedback network should be routed0Zw嘉泰姆
away from the inductor. The feedback pin and feedback network should be shielded with a ground plane0Zw嘉泰姆
or trace to minimize noise coupling into this circuit.0Zw嘉泰姆
5. A star ground connection or ground plane minimizes ground shifts and noise is recommended.0Zw嘉泰姆
八,相关产品                  更多同类产品.......0Zw嘉泰姆

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