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两个低电压降调节器CXSD62114双降压恒定时间同步PWM控制器内部转换MOSFET
发表时间:2020-04-23浏览次数:287
两个低电压降调节器CXSD62114双降压恒定时间同步PWM控制器内部转换MOSFET
 

目录9RW嘉泰姆

1.产品概述                       2.产品特点9RW嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 9RW嘉泰姆
5.产品封装图                     6.电路原理图                   9RW嘉泰姆
7.功能概述                        8.相关产品9RW嘉泰姆

一,产品概述(General Description)    9RW嘉泰姆


  The CXSD62114 integrates dual step-down, constant-on-time,9RW嘉泰姆

synchronous PWM controllers (that drives dual N-channel MOSFETs for9RW嘉泰姆
each channel) and two low drop-out regulators as well as various protections9RW嘉泰姆
into a chip.The PWM controllers step down high voltage of a battery9RW嘉泰姆
to generate low-voltage for NB applications. The output of PWM1 and9RW嘉泰姆
PWM2 can be adjusted from 2V to 5.5V by setting a resistive voltage-divider9RW嘉泰姆
from VOUTx to GND.The linear regulators provide 5V and 3.3V output for9RW嘉泰姆
standby power supply. The linear regulators provide up to 100mA output9RW嘉泰姆
current. When the PWMx output voltage is higher than LDOx bypass threshold, the related LDOx regulator is shut off and its output is connected to VOUTx9RW嘉泰姆
by internal switchover MOSFET. It can save power dissipation. The charge9RW嘉泰姆
pump circuit with 250kHz clock driver uses VOUT1 as its power supply to generate ap-proximately 15V DC voltage.9RW嘉泰姆
  The CXSD62114 provides excellent transient response and accurate DC output voltage in either PFM or PWM Mode. In Pulse-Frequency Mode (PFM),9RW嘉泰姆
the CXSD62114 provides very high efficiency over light to heavy loads9RW嘉泰姆

with loading-modulated switching frequencies. The Forced-PWM Mode works nearly at constant frequency for low-noise requirements. The unique ultrasonic9RW嘉泰姆
mode maintains the switching frequency above 25kHz, which eliminates noise in audio application.The CXSD62114A/D has individual enable controls for9RW嘉泰姆
each PWM channels. Pulling both EN1/2 pin low shuts down the all of outputs unless LDO3 output. The LDO3 and LDO5 of CXSD62114B/C are always on standby power.The CXSD62114 is available in a TQFN3x3-20 package.9RW嘉泰姆
二.产品特点(Features)9RW嘉泰姆


Wide Input voltage Range from 5.5V to 25V9RW嘉泰姆
Provide 5 Independent Outputs with ±1.0% Accu-racy Over-Temperature9RW嘉泰姆
PWM1 Controller with Adjustable (2V to 5.5V) Out-put9RW嘉泰姆
- PWM2 Controller with Adjustable (2V to 5.5V) Out-put9RW嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V Output9RW嘉泰姆
- 100mA Low Dropout Regulator (LDO3) with Fixed 3.3V Output9RW嘉泰姆
250kHz Clock Signal for 15V Charge Pump (Used PWM1 as Its Power Supply)9RW嘉泰姆
Excellent Line/Load Regulations about±1.5% over9RW嘉泰姆
temperature range at PWM Channels9RW嘉泰姆
Low Consumption in Standby Mode9RW嘉泰姆
2Cells Input Battery Support9RW嘉泰姆
Built in POR Control Scheme Implemented9RW嘉泰姆
Constant On-Time Control Scheme9RW嘉泰姆
Built in Soft Start for PWM Outputs and Soft Stop9RW嘉泰姆
for PWM Outputs and LDO Outputs9RW嘉泰姆
Integrated Bootstrap Forward P-CH MOSFET9RW嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)9RW嘉泰姆
Built in Power Good Indicators (PWMs)9RW嘉泰姆
60% Under-Voltage and 115% Over-Voltage Protec-tions (PWM)9RW嘉泰姆
Adjustable Current-Limit Protection (PWMs)9RW嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)9RW嘉泰姆
Over-Temperature Protection9RW嘉泰姆
3mmx3mm Thin QFN-20 (TQFN3x3-20) package9RW嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)9RW嘉泰姆
三,应用范围 (Applications)9RW嘉泰姆


Notebook and Sub-Notebook Computers9RW嘉泰姆
Portable Devices9RW嘉泰姆
DDR1, DDR2, and DDR3 Power Supplies9RW嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered Devices9RW嘉泰姆
Graphic Cards9RW嘉泰姆
Game Consoles9RW嘉泰姆
Telecommunications9RW嘉泰姆
四.下载产品资料PDF文档 9RW嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持9RW嘉泰姆

 QQ截图20160419174301.jpg9RW嘉泰姆

五,产品封装图 (Package)9RW嘉泰姆


blob.png9RW嘉泰姆
blob.png9RW嘉泰姆

六.电路原理图9RW嘉泰姆


blob.png9RW嘉泰姆

七,功能概述9RW嘉泰姆


the node.9RW嘉泰姆
Decoupling capacitor, the resistor dividers, boot capacitors, and current-limit stetting resistor should9RW嘉泰姆
be close to their pins. (For example, place the decoupling ceramic capacitor near the drain of the9RW嘉泰姆
high-side MOSFET as close as possible. The bulk capacitors are also placednear the drain).9RW嘉泰姆
The input capacitor should be near the drain of the upper MOSFET; the high quality ceramic decoupling9RW嘉泰姆
capacitor can be put close to the VCC and GND pins;the output capacitor should be near the loads. The9RW嘉泰姆
input capacitor GND should be close to the output ca-pacitor GND and the lower MOSFET GND.9RW嘉泰姆
The drain of the MOSFETs (V IN and PHASEx nodes)should be a large plane for heat sinking. And PHASEx9RW嘉泰姆
pin traces are also the return path for UGATEx. Con-nect these pins to the respective converter’s upper9RW嘉泰姆
MOSFET source.9RW嘉泰姆
The controller used ripple mode control. Build the re-sistor divider close to the FB1 pin so that the high9RW嘉泰姆
impedance trace is shorter when the output voltage is in ad justable mode. And the FB1 pin traces can’t be9RW嘉泰姆
close to the switching signal traces (UGATEx, LGATEx,BOOTx, and PHASEx).9RW嘉泰姆
The PGND trace should be a separate trace, and in-dependently go to the source of the low-side MOSFETs9RW嘉泰姆
for current-limit accuracy.9RW嘉泰姆
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