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CXSD62113|C双降压恒定开启时间同步的PWM控制器每个通道驱动双N通道mosfet | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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目录 1.产品概述 2.产品特点 一,产品概述(General Description) The CXSD62113 CXSD62113A CXSD62113B CXSD62113C CXSD62113E integrates dual step-down, constant-on-time,synchronous PWM controllers (that drives dual N-channel MOSFETs for each channel) and two low drop-out regulators as well as various protections into a chip.The PWM controllers step down high voltage of a battery to generate low-voltage for NB applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5V by setting a resistive voltage-divider from VOUTx to GND. The linear regulators provide 5V and 3.3V output for standby power supply. The linear regulators provide up to 100mA output current. When the PWMx output voltage is higher than LDOx bypass threshold, the related LDOx regulator is shut off and its output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation. The charge pump circuit with 270kHz clock driver uses VOUT1 as its power supply to generate ap-proximately 15V DC voltage. constant frequency for low-noise requirements. The unique ultrasonic mode maintains the switching frequency above 25kHz, which eliminates noise in Wide Input voltage Range from 6V to 25V Notebook and Sub-Notebook Computers 需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！ 五,产品封装图 (Package)
六.电路原理图
七,功能概述 Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors are remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. MOSFET Selection The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs should be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: · For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET. In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low-side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET will con- duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the power loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET does not have this zero voltage switching condition, and because it conducts for less time compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized. The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitance Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separating and finally combined to use the ground plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout: 八,相关产品 更多同类产品......
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发表时间：2020-04-23浏览次数：69
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