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CXSD62108单相恒定时间同步的脉宽调制控制器驱动N通道mosfet笔记本电脑中产生低压芯片组RAM电源的电压
发表时间:2020-04-23浏览次数:301
CXSD62108单相恒定时间同步的脉宽调制控制器驱动N通道mosfet笔记本电脑中产生低压芯片组RAM电源的电压
 

目录AJR嘉泰姆

1.产品概述                       2.产品特点AJR嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 AJR嘉泰姆
5.产品封装图                     6.电路原理图                   AJR嘉泰姆
7.功能概述                        8.相关产品AJR嘉泰姆

一,产品概述(General Description)         AJR嘉泰姆
      The CXSD62108 is a single-phase, constant-on-time,synchronous PWMAJR嘉泰姆
controller, which drives N-channel MOSFETs. The CXSD62108 steps down highAJR嘉泰姆
voltage to generate low-voltage chipset or RAM supplies in notebook computers.AJR嘉泰姆
      The CXSD62108 provides excellent transient response and accurate DCAJR嘉泰姆
voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM),AJR嘉泰姆
the CXSD62108 provides very high efficiency over light to heavy loads with AJR嘉泰姆

loading-modulated switching frequencies. In PWM Mode, the converter worksAJR嘉泰姆

nearly at constant frequency for low-noise requirements.AJR嘉泰姆
    The CXSD62108 is equipped with accurate positive current-limit, outputAJR嘉泰姆
under-voltage, and output over-voltage protections, perfect for NB applications.AJR嘉泰姆
The Power-On-Reset function monitors the voltage on VCC and PVCC toAJR嘉泰姆
prevent wrong operation during power-on. The CXSD62108 has a 1.2ms digitalAJR嘉泰姆
soft-start and built-in an integrated output discharge device for soft-stop. An AJR嘉泰姆

internal integrated soft-start ramps up the output voltage with programmable AJR嘉泰姆

slew rate to reduce the start-up current. A soft-stop function actively AJR嘉泰姆

discharges the output capacitors.AJR嘉泰姆
       The CXSD62108 is available in 14pin TSSOP, 14pin QFN and 16pin TQFNAJR嘉泰姆
packages respectively.AJR嘉泰姆
二.产品特点(Features)AJR嘉泰姆
Adjustable Output Voltage from +0.75V to +5.5VAJR嘉泰姆
- 0.75V Reference VoltageAJR嘉泰姆
- ±1% Accuracy Over-TemperatureAJR嘉泰姆
Operates from An Input Battery Voltage Range ofAJR嘉泰姆
+1.8V to +28VAJR嘉泰姆
Power-On-Reset Monitoring on VCC Pin and PVCC PinAJR嘉泰姆
Excellent Line and Load Transient ResponsesAJR嘉泰姆
PFM Mode for Increased Light Load EfficiencyAJR嘉泰姆
Programmable PWM Frequency from 100kHz to 500kHzAJR嘉泰姆
Integrated MOSFET DriversAJR嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETAJR嘉泰姆
Adjustable Integrated Soft-Start and Soft-StopAJR嘉泰姆
Selectable Forced PWM or Automatic PFM/PWM ModeAJR嘉泰姆
Power Good MonitoringAJR嘉泰姆
70% Under-Voltage ProtectionAJR嘉泰姆
125% Over-Voltage ProtectionAJR嘉泰姆
Adjustable Current-Limit ProtectionAJR嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)AJR嘉泰姆
Over-Temperature ProtectionAJR嘉泰姆
TSSOP-14, QFN3.5x3.5-14, and TQFN3x3-16 PackagesAJR嘉泰姆
Lead Free and Green Devices Available (RoHS Compliant)AJR嘉泰姆
三,应用范围 (Applications)AJR嘉泰姆
NotebookAJR嘉泰姆
Table PCAJR嘉泰姆
Hand-Held PortableAJR嘉泰姆
AIO PCAJR嘉泰姆
四.下载产品资料PDF文档 AJR嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持AJR嘉泰姆

 QQ截图20160419174301.jpgAJR嘉泰姆

五,产品封装图 (Package)AJR嘉泰姆

blob.pngAJR嘉泰姆

六.电路原理图AJR嘉泰姆


blob.pngAJR嘉泰姆
七,功能概述AJR嘉泰姆


Layout Consideration (Cont.)AJR嘉泰姆
· The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and dis-AJR嘉泰姆
charging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide.AJR嘉泰姆
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-AJR嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. InAJR嘉泰姆
addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can get better heatAJR嘉泰姆
sinking.AJR嘉泰姆
· The PGND is the current sensing circuit reference ground and also the power ground of the LGATE low-AJR嘉泰姆
side MOSFET. On the hand, the PGND trace should be a separate trace and independently go to the source of theAJR嘉泰姆
low-side MOSFET. Besides, the current sense resistor should be close to OCSET pin to avoid parasitic capaci-AJR嘉泰姆
tor effect and noise coupling.AJR嘉泰姆
· Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, placeAJR嘉泰姆
the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)AJR嘉泰姆
· The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitorsAJR嘉泰姆
should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitorsAJR嘉泰姆
and low-side MOSFET.AJR嘉泰姆
· Locate the resistor-divider close to the FB pin to mini-mize the high impedance trace. In addition, FB pin tracesAJR嘉泰姆
can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE).AJR嘉泰姆
八,相关产品                      更多同类产品...... AJR嘉泰姆


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