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CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V
发表时间:2020-04-22浏览次数:125
CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V
 

目录EC4嘉泰姆

1.产品概述                       2.产品特点EC4嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 EC4嘉泰姆
5.产品封装图                     6.电路原理图                   EC4嘉泰姆
7.功能概述                        8.相关产品EC4嘉泰姆

一,产品概述(General Description)         EC4嘉泰姆

        The CXSD62104  integrates dual step-down, constant-ontime, synchronousEC4嘉泰姆

PWM controllers (that drives dual N-channel MOSFETs for each channel) andEC4嘉泰姆
two low drop-out regulators as well as various protections into a chip.The PWMEC4嘉泰姆
controllers step down high voltage of a battery to generate low-voltage for NBEC4嘉泰姆
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5VEC4嘉泰姆
by setting a resistive voltage-divider from VOUTx to GND.The linear regulatorsEC4嘉泰姆
provide 5V and 3.3V output for standby power supply. The linear regulatorsEC4嘉泰姆

provide up to 100mA output current. When the PWMx output voltage is higher EC4嘉泰姆

than LDOx bypass threshold, the related LDOx regulator is shut off and its EC4嘉泰姆

output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.EC4嘉泰姆
     The CXSD62104 provides excellent transient response and accurate DC EC4嘉泰姆

output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), EC4嘉泰姆

the CXSD62104 provides very high efficiency over light to heavy loads with EC4嘉泰姆

loading-modulated switching frequencies. The Forced-PWM mode works nearly EC4嘉泰姆

at constant frequency for low-noise requirements. The unique ultrasonic modeEC4嘉泰姆

 maintains the switching frequency above 25KHz, which eliminates noise in audio applications.EC4嘉泰姆

     The CXSD62104 is equipped with accurate sourcing cur-rent-limit, outputEC4嘉泰姆

under-voltage and output over-voltage protections, being perfect for NB EC4嘉泰姆

applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. EC4嘉泰姆

A soft-stop function actively discharges the output capaci-tors by the discharge EC4嘉泰姆

device. The CXSD62104 has individual enable controls for PWM channels and EC4嘉泰姆

LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chipEC4嘉泰姆

with low quiescent current close to zero.EC4嘉泰姆
      The CXSD62104 is available in a TQFN4x4-24A package.EC4嘉泰姆
二.产品特点(Features)EC4嘉泰姆
Wide Input Voltage Range from 6V to 25VEC4嘉泰姆
Provide 4 Independent Outputs with ±1.5% Accu-EC4嘉泰姆
racy Over-TemperatureEC4嘉泰姆
- PWM1 Controller with Adjustable (2V to 5.5V) Out-putEC4嘉泰姆
PWM2 Controller with Adjustable (2V to 5.5V) Out-putEC4嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V OutputEC4嘉泰姆
100mA Low Dropout Regulator (LDO3) with Fixed 3.3V OutputEC4嘉泰姆
Excellent Line/Load Regulations about ±1.5% Over-Temperature RangeEC4嘉泰姆
±1%, (±1.5%, 50μA) 2.0V Reference Voltage OutputEC4嘉泰姆
Built-In POR Control Scheme ImplementedEC4嘉泰姆
Selectable Forced-PWM or Automatic PFM/PWMEC4嘉泰姆
(with Selectable Ultrasonic Operation)EC4嘉泰姆
Constant-On-Time Control Scheme with FrequencyEC4嘉泰姆
Compensation for PWM ModeEC4嘉泰姆
Selectable Switching Frequency in PWM ModeEC4嘉泰姆
Built-in Digital Soft-Start for PWM Outputs and Soft-EC4嘉泰姆
Stop for PWM Outputs and LDO OutputsEC4嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETEC4嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)EC4嘉泰姆
Built-in Power Good Indicators (PWMs)EC4嘉泰姆
Independent Enable Inputs (PWMs, LDO)EC4嘉泰姆

70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM)EC4嘉泰姆

Adjustable Current-Limit Protection (PWMs)EC4嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)EC4嘉泰姆
Over-Temperature ProtectionEC4嘉泰姆
4mmx4mm Thin QFN-24 (TQFN4x4-24A) packageEC4嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)
EC4嘉泰姆

三,应用范围 (Applications)EC4嘉泰姆

Notebook and Sub-Notebook ComputersEC4嘉泰姆

Portable DevicesEC4嘉泰姆
DDR1, DDR2, and DDR3 Power SuppliesEC4嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered DevicesEC4嘉泰姆
Graphic CardsEC4嘉泰姆
Game ConsolesEC4嘉泰姆
Telecommunications
EC4嘉泰姆

四.下载产品资料PDF文档 EC4嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持EC4嘉泰姆

 QQ截图20160419174301.jpgEC4嘉泰姆

五,产品封装图 (Package)EC4嘉泰姆


blob.pngblob.pngEC4嘉泰姆

六.电路原理图EC4嘉泰姆


blob.pngEC4嘉泰姆

七,功能概述EC4嘉泰姆


Input Capacitor SelectionEC4嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selectEC4嘉泰姆
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMSEC4嘉泰姆
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors areEC4嘉泰姆
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-EC4嘉泰姆
side MOSFET with very low-impeadance PCB layout. EC4嘉泰姆
MOSFET SelectionEC4嘉泰姆
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs shouldEC4嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:EC4嘉泰姆
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFETEC4嘉泰姆
driver will not charge the miller capacitor of this MOSFET.EC4嘉泰姆
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. TheEC4嘉泰姆
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driverEC4嘉泰姆
sinking current path. This results in much less switching loss of the low-side MOSFETs. The dutyEC4嘉泰姆
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-EC4嘉泰姆
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the powerEC4嘉泰姆
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFETEC4嘉泰姆
does not have this zero voltage switching condition, and because it conducts for less timeEC4嘉泰姆
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be givenEC4嘉泰姆
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.EC4嘉泰姆
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitanceEC4嘉泰姆
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-EC4嘉泰姆
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given byEC4嘉泰姆
the following equations:EC4嘉泰姆
Layout ConsiderationEC4嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.EC4嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike acrossEC4嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionEC4嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,EC4嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasiticEC4嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short andEC4嘉泰姆
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. AndEC4嘉泰姆
signal and power grounds are to be kept separating and finally combined to use the ground plane construction orEC4嘉泰姆

single point grounding. The best tie-point between the signal ground and the power ground is at the negativeEC4嘉泰姆
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are notEC4嘉泰姆
recommended. Below is a checklist for your layout:EC4嘉泰姆
Layout Consideration (Cont.)EC4嘉泰姆
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodesEC4嘉泰姆
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes asEC4嘉泰姆
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.EC4嘉泰姆

Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce ofEC4嘉泰姆

CXSD62104EC4嘉泰姆

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CXSD6274CEC4嘉泰姆

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VMEC4嘉泰姆

1EC4嘉泰姆

1EC4嘉泰姆

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1EC4嘉泰姆

1EC4嘉泰姆

20EC4嘉泰姆

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13.2EC4嘉泰姆

0.8EC4嘉泰姆

5~12EC4嘉泰姆

2100EC4嘉泰姆

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13.2EC4嘉泰姆

0.8EC4嘉泰姆

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1EC4嘉泰姆

1EC4嘉泰姆

5EC4嘉泰姆

5EC4嘉泰姆

13.2EC4嘉泰姆

1.25|0.8EC4嘉泰姆

5~12EC4嘉泰姆

3000EC4嘉泰姆

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VMEC4嘉泰姆

1EC4嘉泰姆

1EC4嘉泰姆

10EC4嘉泰姆

3.3EC4嘉泰姆

5.5EC4嘉泰姆

0.8EC4嘉泰姆

5EC4嘉泰姆

2100EC4嘉泰姆

CXSD6279BEC4嘉泰姆

SOP-14EC4嘉泰姆

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1EC4嘉泰姆

1EC4嘉泰姆

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13.2EC4嘉泰姆

0.6EC4嘉泰姆

5~12EC4嘉泰姆

4000EC4嘉泰姆

CXSD6281NEC4嘉泰姆

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1EC4嘉泰姆

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1EC4嘉泰姆

1EC4嘉泰姆

30EC4嘉泰姆

2.2EC4嘉泰姆

13.2EC4嘉泰姆

0.6EC4嘉泰姆

12EC4嘉泰姆

5000EC4嘉泰姆

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1EC4嘉泰姆

1EC4嘉泰姆

30EC4嘉泰姆

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0.6EC4嘉泰姆

12EC4嘉泰姆

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